Field of the Invention
The present invention relates to a differential circuit.
Description of Related Art
Conventionally, there is known a differential circuit, which outputs a current corresponding to a difference between two input voltages. FIG. 14 illustrates an example of a conventional differential circuit.
A conventional differential circuit DF100 illustrated in FIG. 14 includes transistors 101 to 108 and a constant current circuit 109. Sources of the transistors 101 and 102, which are P-channel MOS field effect transistors (MOSFETs) forming a differential pair, are connected to an application terminal of a power supply voltage via the constant current circuit 109. An input voltage Vp is applied to a gate of the transistor 101, and an input voltage Vm is applied to a gate of the transistor 102.
The transistor 103 as an N-channel MOSFET having short-circuited drain and gate and the transistor 104 as an N-channel MOSFET constitute a first current mirror, and the drain of the transistor 103 is connected to a drain of the transistor 101. Sources of the transistors 103 and 104 are connected to a ground terminal.
The transistor 105 as an N-channel MOSFET having short-circuited drain and gate and the transistor 106 as an N-channel MOSFET constitute a second current mirror, and the drain of the transistor 102 is connected to a drain of the transistor 105. Sources of the transistors 105 and 106 are connected to the ground terminal.
The transistor 107 as a P-channel MOSFET having short-circuited drain and gate and the transistor 108 as a P-channel MOSFET constitute a third current mirror, the drain of the transistor 107 is connected to a drain of the transistor 106, and a drain of the transistor 108 is connected to a drain of the transistor 104. Sources of the transistors 107 and 108 are connected to the application terminal of the power supply voltage. A connection node between the drain of the transistor 108 and the drain of the transistor 104 is connected to an output terminal Tout.
Drain currents flow in the transistors 101 and 102 in accordance with a ratio between input voltages Vp and Vm. Further, an output current I101 flows by the first current mirror in accordance with an input of the drain current flowing in the transistor 101. Further, an output current I102 flows by the second current mirror and the third current mirror in accordance with an input of the drain current flowing in the transistor 102.
Essentially, if the input voltage Vp is the same as the input voltage Vm, the output current I101 and the output current I102 are balanced, and no current is output from the output terminal Tout. Actually, however, a balance between the output current I101 and the output current I102 may be lost due to characteristic variations of the transistors 101 and 102 forming the differential pair. In other words, a current may be output from the output terminal Tout so that an offset may occur.
Accordingly, it is considered to suppress the characteristic variations so as to suppress the offset by increasing gate widths of the transistors Vp and Vm and/or by decreasing gate lengths of the same so as to increase gains. However, in this case, there is a problem that response speeds are decreased when the gains are increased so that mirror capacitances are increased.
Accordingly, as illustrated in FIG. 15, for example, a structure including a constant current circuit 110, transistors 111 and 112, and resistors 113 and 114 may be disposed in the preceding stage of the transistors 101 and 102 illustrated in FIG. 14, and in the further preceding stage thereof, a structure including a constant current circuit 115, transistors 116 and 117, and resistors 118 and 119 may be disposed, so as to adopt a multi-stage structure in which the input voltage Vp is applied to a gate of the transistor 116, and the input voltage Vm is applied to a gate of the transistor 117. In this way, it is possible to increase a total gain while the gain of each transistor is decreased so that a mirror capacitance is decreased. However, there is a problem that the number of elements is increased.
Note that JP-A-2009-156835 (particularly, FIG. 5) discloses a conventional example of an over current protection circuit using a differential circuit having a structure in which bipolar transistors are used, but this document does not suggest suppressing the characteristic variation by setting gate sizes of the MOSFETs as described above and the accompanying problem of response speeds.
In addition, another example of the conventional differential circuit is illustrated in FIG. 16.
The conventional differential circuit illustrated in FIG. 16 includes a transistor 126 and a transistor 127 as P-channel MOS field effect transistors (MOSFETs) forming a differential pair. Sources of the transistors 126 and 127 are connected to a constant current circuit 125. A transistor 128 as an N-channel MOSFET having short-circuited drain and gate and a transistor 129 as an N-channel MOSFET constitute a current mirror, and the drain of the transistor 128 is connected to a drain of the transistor 126.
In addition, a transistor 130 as an N-channel MOSFET having short-circuited drain and gate and a transistor 131 as an N-channel MOSFET constitute a current mirror, and the drain of the transistor 130 is connected to a drain of the transistor 127. A transistor 132 as a P-channel MOSFET having short-circuited gate and drain and a transistor 133 as a P-channel MOSFET constitute a current mirror, and the drain of the transistor 132 is connected to a drain of the transistor 131. The output terminal Tout from which a current is output is connected to a connection node between a drain of the transistor 133 and a drain of the transistor 129.
In addition, a series circuit including a constant current circuit 123, a variable resistor VR1, and a transistor 121 as a P-channel MOSFET is disposed in association with the transistor 126. A gate of the transistor 126 is connected to a connection node between the constant current circuit 123 and the variable resistor VR1. Similarly, a series circuit including a constant current circuit 124, a variable resistor VR2, and a transistor 122 as a P-channel MOSFET is disposed in association with the transistor 127. A gate of the transistor 127 is connected to a connection node between the constant current circuit 124 and the variable resistor VR2.
Essentially, if the same input voltage is applied to the gates of the transistors 126 and 127 forming the differential pair, a drain current I121 flowing in the transistor 129 and a drain current I122 flowing in the transistor 133 are balanced due to the structure of the current mirrors described above, and no current is output from the output terminal Tout. Actually, however, a balance between the drain current I121 and the drain current I122 may be lost due to manufacturing variations of the transistors 126 and 127, and a current may be output from the output terminal Tout. In other words, an offset may occur. Note that the current flows out from the output terminal Tout or flows in from the outside depending on the balance between the drain current I121 and the drain current I122.
Accordingly, in the differential circuit illustrated in FIG. 16, the above-mentioned series circuits are disposed with respect to the transistors 126 and 127, and resistance values of the variable resistors VR1 and VR2 are adjusted in the state where the same input voltage is applied to gates of the transistors 121 and 122. Thus, gate voltages of the transistors 126 and 127 are adjusted so that the balance between the drain current I121 and the drain current I122 is adjusted, and hence current output from the output terminal Tout is prevented (namely, the offset does not occur). This offset adjustment is performed when shipping from a factory or in other occasion.
Note that an example of a conventional technique related to the above description is disclosed in JP-A-2013-030830.
However, the above-mentioned differential circuit illustrated in FIG. 16 requires power supply voltage considering two-stage voltage including a gate-source voltage of the transistor 121 and a gate-source voltage of the transistor 126 with respect to the input voltage of the transistor 121 (the same is true for the transistor 122), which is not desired in a recent situation where a lower power supply voltage for devices has been proceeding.